pouët.net

The ASM instruction you always wanted, but never had?

category: code [glöplog]
Which instructions would you add to a z80, 6502 or similar 8-bit CPU if you had the chance?
added on the 2010-07-12 17:45:30 by trc_wm trc_wm
barrel shifter
added on the 2010-07-12 17:50:08 by kusma kusma
affine texture mapping innerloop fragments
added on the 2010-07-12 17:58:25 by arm1n arm1n
spike: that is rather broad, can you be more specific?
added on the 2010-07-12 17:59:35 by trc_wm trc_wm
Faster index register instructions for Z80, but ofcourse not necessary.
added on the 2010-07-12 18:01:00 by MuffinHop MuffinHop
Code: dec ecx jns label


=>
Code: loopns label
added on the 2010-07-12 18:23:59 by las las
I was thinking about
Code: movnz r0,r1
which transfers r1 to r0 only when r1 is not zero. Nice for blitting sprites.
added on the 2010-07-12 18:31:53 by trc_wm trc_wm
For the Z80:
- Fast clear memory instruction (like LDIR but faster and with (HL) replaced by an immediate value)
- Register rotation and shift of n bits in one pass
- Bit change (like RES and SET but with a XOR 1 effect)
- Multiplication but that's pushing things a bit too far :)
A multiplier will hardly be noticed (size wise) in a Z80, given the current dimension of transistors these days. The 8-bit ATmega series has multipliers, so putting one into a beefed-up Z80 is not so far-fetched.

In fact, the HD64180, which is a beefed-up Z80, has an onboard multiplier. That thing came out around 1985!
added on the 2010-07-12 18:57:35 by trc_wm trc_wm
+1 for the index register instruction as well
added on the 2010-07-12 18:58:18 by kusma kusma
I see what you mean.. Index instructions take 5 to 6 M-cycles and M-cycles are 3 to 6 clock cycles.. That thing is as slow as shit through a funnel.
added on the 2010-07-12 19:01:27 by trc_wm trc_wm
The eZ80 is much better in that respect.
added on the 2010-07-12 19:04:45 by trc_wm trc_wm
T80 soft CPU, that you can use in an FPGA-based computer, adds T-states artificially to imitate the real Z80 and 8080. Just by removing extra T-states it can be made much faster even at the same clock speed. Using static RAM is another speeding factor. Adding instructions is very much possible, too.
added on the 2010-07-12 19:09:11 by svo svo
movbrain rrrola,ME
added on the 2010-07-12 19:37:53 by ferris ferris
unpckxchg49bandcmpunlck
added on the 2010-07-12 19:45:01 by ponce ponce
omgwtfbbq
added on the 2010-07-12 19:52:56 by Joghurt Joghurt
65c816's stz would also be nice on a 6502
added on the 2010-07-12 19:54:04 by ferris ferris
@svo: I've seen the T80; pretty nifty! Love your steam engine BTW.
added on the 2010-07-12 19:58:38 by trc_wm trc_wm
OMG, which should be a half NOP ... nah :)
On a 6502 I could do with this kind of improvement:
- an instruction to set the address of the stack, would make it possible to use PHA/PLA anywhere in memory :)
- as Ferris wrote, STZ would be a nice addition, as well as TXY and TYX.
- a variant of INC and DEC (INA/DEA) working on the A register could be nice
- a new flag to disable the usage of the carry when using ROL and ROR (to have 8 bits rotations instead of 9 bits)
added on the 2010-07-12 20:15:42 by Dbug Dbug
What Dbug said, plus a half nop like Weyland said.
added on the 2010-07-12 20:24:47 by ferris ferris
dbug, I believe the 65c816 has txy and tyx. Anyway, my instruction would be XCQ: Exchange Carry and Quantum bit.
render3dscene

added on the 2010-07-12 20:36:44 by xeron xeron
also:

print_real_edible_pizza_from_printer
added on the 2010-07-12 20:37:14 by xeron xeron
Nah, that needs some improvement xeron.

mov al,3
print_real_edible_pizzas_from_printer al
added on the 2010-07-12 20:46:11 by sigflup sigflup

login